1. Field of the Invention
The present invention relates to a liquid crystal display device and display apparatus, and particularly to a liquid crystal display device of a fringe field switching (FFS) mode (referred to also as an in-plane switching (IPS)-Pro mode) and display apparatus including the liquid crystal display device.
2. Description of the Related Art
In an FFS-mode liquid crystal display device, a common electrode and pixel electrodes for applying to a liquid crystal layer a lateral electric field substantially parallel to the substrate surface are provided on the same substrate side, and liquid crystal elements are driven by this lateral electric field for image displaying. An FFS-mode liquid crystal display device of a related art will be described below with reference to FIG. 14. The sectional view of FIG. 14A is along line A-A′ in FIG. 14B.
The liquid crystal display device shown in this drawing is transmissive one. This liquid crystal display device includes a liquid crystal panel that is formed of a first substrate 110, a second substrate 120 disposed to face the element-formed surface of the first substrate 110, and a liquid crystal layer 130 interposed between these first and second substrates 110 and 120. Furthermore, in this liquid crystal panel, polarizers 140 and 150 are provided in tight contact with the outside surfaces of the first substrate 110 and the second substrate 120, respectively. Further outside the polarizer 140 on the first substrate 110, a backlight (not shown) serving as a light source for transmissive displaying is provided.
The first substrate 110 is formed of a transparent substrate such as a glass substrate. Over the surface thereof facing the liquid crystal layer 130, plural scan lines 111 and plural signal lines 112 are arranged in a matrix. At each of the intersections between the scan lines 111 and the signal lines 112, a drive element formed of a thin film transistor (TFT) 1 for driving a respective one of the pixels is provided. The area surrounded by the scan lines 111 and the signal lines 112 serves as a pixel area 110A.
Between the scan line 111 and the next scan line 111 for an adjacent pixel, a common potential line 113 is provided close to the scan line 111 for the adjacent pixel in parallel to the scan lines 111. Furthermore, on the same plane, a common electrode 114 is provided in the pixel area 110A except the formation area of the TFT 1 in such a way that one end of the common electrode 114 overlaps with the common potential line 113. This common electrode 114 is provided on the same plane as that of the scan line 111, and therefore the arrangement of the common electrode 114 is limited by the scan line 111.
A gate electrode 2 of the TFT 1 is formed of a partial portion of the scan line 111. On the first substrate 110, a gate insulating film 3 is provided to cover the scan line 111, the common potential line 113, and the common electrode 114. Moreover, a semiconductor layer 4 is pattern-formed on the gate insulating film 3 covering the gate electrode 2.
The partial portion of the semiconductor layer 4 directly above the gate electrode 2 serves as a channel layer 4a. On both the sides of the channel layer 4a, a source region 4b and a drain region 4c that contain an n-type impurity are provided. On the source region 4b, a source electrode 6a is so disposed as to be connected to the source region 4b, and the source electrode 6a is connected to the signal line 112. On the drain region 4c, a drain electrode 6b is so disposed as to be connected to the drain region 4c. The TFT 1 is formed in this manner.
On the gate insulating film 3, an interlayer insulating film 115 is provided to cover the TFT 1. In this interlayer insulating film 115, a contact hole 115a reaching the drain electrode 6b of the TFT 1 is provided. On the interlayer insulating film 115, a pixel electrode 116 that is connected via this contact hole 115a to the TFT 1 and has plural slits 116a is provided. These slits 116a are in parallel to the scan lines 111. Furthermore, an alignment layer 117 is provided on the interlayer insulating film 115 and covers the pixel electrode 116.
Due to this structure, an electric field is generated between the common electrode 114 and the ends of electrode portions of the pixel electrode 116, which sandwich the slits 116a. Thus, a lateral electric field substantially parallel to the substrate surface is applied to the liquid crystal layer 130.
The second substrate 120 is also formed of a transparent substrate such as a glass substrate. Over the surface thereof facing the liquid crystal layer 130, a color filter 121 for the respective colors of red (R), green (G), and blue (B) and an alignment layer 122 are provided in that order.
In the liquid crystal display device having the above-described structure, the scan line 111 and the common electrode 114 are disposed on the same plane of the first substrate 110, and therefore the formation area of the common electrode 114 is limited by the scan line 111. This leads to problems of a low aperture ratio and low transmittance.
To address the problems, there has been reported an example of a liquid crystal display device obtained by, in the structure of the liquid crystal display device described above by using FIG. 14, disposing the pixel electrode 116 having the slits 116a on the gate insulating film 3 and disposing the common electrode 114 on the interlayer insulating film 115 (refer to e.g. Japanese Patent No. 3742837 (Patent document 1)).
Furthermore, there has also been reported an example in which the common electrode 114 is disposed on the gate insulating film 3 in the structure of the liquid crystal display device described above by using FIG. 14 (refer to e.g. Japanese Patent No. 3740514 and Japanese Patent No. 3742836 (Patent documents 2 and 3)).
However, in the liquid crystal display device described in Patent document 1, although there is no limitation on the arrangement of the common electrode 114, it is difficult to apply an electric field parallel to the substrate surface because the pixel electrode 116 having the slits 116a is not disposed close to the liquid crystal layer 130. Thus, it is impossible to control the liquid crystal layer 130, and hence the liquid crystal displaying itself is difficult.
Furthermore, in the liquid crystal display device described in Patent documents 2 and 3, the arrangement of the common electrode 114 is limited by the signal line 112, and therefore it is difficult to keep a high aperture ratio.
To address these problems, it would be possible that, as shown in the plan view of FIG. 15A, a pixel electrode 116′ that is so formed as to have a larger size on the signal line sides compared with the common electrode 114 is disposed to overlap with the signal lines 112. However, in this structure, as shown in the circuit diagram of FIG. 15B, parasitic capacitances C1 and C2 are generated between the signal line 112 and the pixel electrode 116′, which causes vertical crosstalk.